The design methodology for electronic circuit designs, in particular complex integrated circuit (IC) designs, has evolved with the advancement in process technologies. Currently, hardware description languages (HDL) are widely used to describe the behavioral and structural design of an electronic circuit at different levels of abstraction. HDL languages are for example Verilog (IEEE-STD1364), SystemVerilog (IEEE-STD1800) or VHDL (Very high speed integrated circuit Hardware Description Language defined by IEEE-STD1076) to describe the circuit at register-transfer level (RTL). A computer-aided design (CAD) tool, generally also called logic synthesizer, is then used to transform the above behavioral and structural description in a HDL into a technology dependent gate-level netlist, taking into account user-specified constraints on timing, power, area, etc.
The design of electronic circuits needs to be verified in order to prove for their proper functionality. With the ever-growing complexity of circuits, the verification cost has become a significant portion of the total development cost. Hence, verification issues should be taken seriously in the design process. Simulation environments are used to verify the abstracted designs using simulation models to represent circuits that interface to the designs. Such collection of simulation models is commonly called a testbench environment.